ADC with Computational modes
Check out this project's MPLAB Xpress Webpage to view the complete code example along with a detailed step by step write-up and description, or visit the PIC18F25Q10 Device Product Page for more information.
About this Code Example
The PIC18FxxQ10 family of devices are equipped with a 10-bit ADC with Computation (ADCC) automating Capacitive Voltage Divider (CVD) techniques for advanced touch sensing, averaging, filtering, oversampling and performing automatic threshold comparisons.
Features of ADCC:
- Thirty-five external channels and four internal analog channels
- Conversion available during sleep, if FRC clock is used
- Auto conversion trigger
- Internal and external trigger options
- Interrupts upon completion of a conversion or threshold comparison
- Automated math functions on input signals, integrated in the hardware
- Averaging, filter calculations, oversampling and threshold comparison
These MCUs also contains hardware limit timer (HLT) which is enhanced version of timer2 with asynchronous operation and reset, start or stop capability from external/internal signal sources. The HLT can be operated in various modes such as one shot, monostable, roll over pulse mode etc.
The PIC18F25Q10 (28-pin, SPDIP package) MCU is used in this demo along with curiosity HPC board and USB-UART click board.
This demo demonstrates the usage of ADCC module with different computation modes such as basic, average, burst average and low pass filter mode for sensing applications.
The basic mode is considered as ‘legacy’ mode since it does not use the computation features, like a typical ADC module available in many PIC16 and PIC18 devices.
In average mode, the ADCC module accumulates one sample for each auto conversion trigger. The ADCC module accumulates a certain number of samples (depending upon ADRPT value) and computes average of the accumulated value.
In burst average mode, the ADCC module accumulates a certain number of samples (depending upon ADRPT value) sequentially at a single stretch for each auto conversion trigger and computes average of the accumulated value.
The Low-Pass Filter mode filters unwanted frequencies from the input signal. In Low-pass filter mode, the ADCC allows the signals whose frequencies are below the cut-off frequency and attenuate signals with frequencies above the cut-off frequency.
After completion of ADC conversion and computation, the computed data is sent to data visualizer tool over USB-UART bridge. Using the data visualizer, the users can visualize ADC data either on terminal window or oscilloscope window.
The computation modes of ADC module are user selectable and changes upon detection of a switch press event. Hardware Limit Timer (HLT) module of the MCU is an Core Independent Peripheral (CIP) and is used for implementing switch de-bounce mechanism. The switch de-bounce mechanism with HLT module functions without the need of a code implementation other than setting up the module using MPLAB® Code Configurator (MCC).
Data Acquisition using ADCC:
The figure below shows block diagram view of the demo application.
Block Diagram - Data Acquisition using ADCC
The Curiosity High Pin Count (HPC) development board has got a potentiometer and is connected to analog input (RA0). The potentiometer generates input signal for the ADCC module in basic, average, and burst-average computation modes. For Low-Pass filter mode, a function generator is required to generate input signal on the analog input (RA1).
After power up, by default the ADCC operates in basic mode. Switch (S2) on the board is useful to select appropriate ADC computation mode, and LEDs D2 and D3 are used to indicate the ADCC computation mode.The table below shows the state of LEDs when a specific computation mode is selected.
|Computation Mode||LED D3||LED D2|
The ADCC module of PIC18F25Q10 MCU periodically acquires analog data and process it to equivalent digital data. The timer0 module acts as a source of trigger to initiate the ADC auto conversion. The interval for the timer can be varied to achieve different ADC sampling frequencies. In case of basic, average and burst-average modes, the sampling frequency is set to 100Hz. Whereas in case of low-pass filter mode, the interval is selected to 1msec to generate a sampling frequency of 1KHz.
In Low-pass filter mode, cut-off frequency is calculated as below:where,
T is the sampling frequency
radian value @ -3 dB is chosen according to the below table
|ADCRS||ωT (radians) @ -3 dB Frequency||dB @ Fnyquist = 1/(2T)|
In the demo, configured timer period T = 1ms and ADCRS = 3.
Therefore, f(cutoff) = 0.134 / (2 * π * 1ms) = 21.3 Hz.
On the Curiosity HPC board, the switch S2 is connected to pin RC5 of the MCU and the switch is of type momentary SPST. De-bouncing mechanism is required to detect the valid switch activation/press event. The switch de-bounce mechanism eliminates the spurious state changes on the pin RC5 (connected to switch) due to electrical noise. The HLT module (timer4) is configured with a periodicity of 10msec for the de-bounce mechanism.
The switch de-bounce mechanism is applicable for both the switch press and release events. The pin RC5 state transitions from High-to-Low when the switch is pressed and Low-to-High when the switch is released. The HLT module gets activated after detection of either High-to-Low or Low-to-High transition on the pin. After the 10mesc period is elapsed, the HLT module generates an output pulse. Upon detection of one cycle of switch press and release events, the firmware checks for pin RC5 state high and then changes the ADC operating mode.
In all the computation modes, the ADCC’s conversion results are transmitted to data visualizer tool over the UART interface and using the USB-to-UART Click board. The data visualizer tool is useful to analyze the ADCC data.
Make sure that the latest software libraries are installed. The demo/example uses the following version of software tools from Microchip.
- MPLAB Code Configurator (Plugin) version: 3.55.1
- MCC Core version: 4.45
- Microcontrollers and peripherals Library version: 1.65.2
- MikroElektronika Click Library version: 1.0.26
- Data Visualizer (Standalone) version: 2.16.661
Data visualizer setup:
Data Visualizer is a program useful for processing and visualizing data. Data Visualizer can receive data from COM ports and various other sources such as the Embedded Debugger Data Gateway Interface found on Xplained Pro boards. Data Visualizer has a graph plotter and an oscilloscope, a terminal and a configurable dashboard with buttons, sliders, and various indicators. It can decode protocols and log data to file.
For more information, refer the data visualizer user guide. It can be downloaded from here
Download the latest version of data visualizer (standalone) from here
Selected 64 MHz as system clock by configuring RSTOSC as HFINTOSC with HFFRQ = 64MHz and CDIV = 1:1.
Timer 0 configuration for ADCC's Basic, Average and Burst-average modes:
Selected timer clock source as FOSC/4. The clock prescaler is set to 1:8192. Set timer period as 10msec to trigger ADC conversion after every 10msec and to achieve ADC sampling frequency of 100Hz.
ADCC configuration for basic mode:
The ADC operating mode is selected as Basic mode. The ADC clock source is configured as FOSC/ADCLK with ADC clock of FOSC/64. The auto conversion trigger source is selected as Timer 0. Enabled ADC threshold interrupt (to keep the same ISR for all the modes).
ADCC configuration for average mode:
The ADC operating mode is selected as Average mode. Enabled ADC threshold interrupt.
In “Computation Feature” tab, configured error calculation parameter as “Actual result vs set point”. For threshold comparison, “Set point” parameter is configured to 511, lower threshold parameter is configured to -200 and upper threshold parameter is configured to 200. The threshold interrupt gets generated whenever the value is above lower threshold and below upper threshold, otherwise error flag gets set.
The repeat count selected as 16 to accumulate 16 ADC samples and average them to get the average result in ADFLT register by right shifting the accumulator by 4 positions.
ADCC configuration for burst average mode:
The ADC operating mode is selected as “Burst Average mode”. All the remaining parameters are configured same as in the average mode.
When compared with average mode the major difference in burst average mode is, for each trigger event the ADCC module accumulates ADRPT number of samples sequentially (at a single stretch) and then calculates average of the accumulated value. This allows for a threshold comparison on the average of a short burst of ADC samples.
ADCC configuration for Low pass filter mode:
The ADC operating mode is selected as Low Pass Filter mode. The ADCRS value is selected as 3 for low-pass filter cutoff frequency of 21.33Hz with ADC sampling frequency of 1KHz.
Timer 0 configuration for ADCC's low pass filter mode:
The timer period is set to 1msec for triggering ADC conversion every 1msec and to achieve ADC sampling frequency of 1KHz.
Timer 4 (HLT) configuration for switch de-bounce:
The timer4 module Clock Source is selected as LFINTOSC with Prescaler set to 1:2. Timer Period is configured to 10msec. Ext Reset Source parameter is configured as T4CKIPPS pin, which is connected to pin RC5. Control Mode parameter is configured as Monostable. In monostable mode, the timer generates an output pulse after the 10msec period is elapsed. Start/Reset Option is configured as “Starts on rising/falling edge on TMR4_ers” (TMR4 external reset source), which indicates start the timer upon detection of either of the edges.
Set the UART Baud Rate to 115200. Enabled both Transmit and Receive parameters. Also, enabled ESUART interrupt.
Full pin settings:
Pin RA0 is used as analog input for the potentiometer. Pin RA1 is used as analog input where function generator is connected.
Switch S2 is connected to pin RC5, which is used as input source to timer4 (HLT) module to initiate the de-bounce check mechanism after a switch press or release event.
- Connect USB-UART click board in microBUS slot 1 of the curiosity HPC board.
- The following table shows port pins of PIC18F25Q10 MCU configured in this application along with its respective signal names.
|1||RA0/AN0||Potentiometer||Curiosity HPC board|
|2||RA1/AN1||Analog Input||Curiosity HPC board|
|3||RA4||LED D2||Curiosity HPC board|
|4||RA5||LED D3||Curiosity HPC board|
|5||RC5||Switch S2||Curiosity HPC board|
|6||RC6/TX||UART TX||USB-UART Click|
|7||RC7/RX||UART RX||USB-UART Click|
- Connect function generator’s output to pin RA1 (on header J8) of curiosity HPC board. Establish common ground reference for both function generator and curiosity HPC board.
Connect USB mini cable between PC and USB-UART click board.
Power on the curiosity HPC board using USB micro cable connected to the PC.
Program the PIC18F25Q10 device on curiosity HPC board using onboard programmer.
Open the configuration tab of data visualizer tool.
- The configuration tab shows the various available options. Select Serial Port from the configuration tab.
Serial Port Configuration:
a). After connecting the USB-UART click to PC, select the COM port from the drop-down menu
b). Select baud rate as 115200
c). Click on "Connect" option, then the terminal window opens
- By default, the ADCC is configured in basic mode. No computational feature is enabled and the raw data is displayed in the terminal window.
- Press switch (S2) on the board, the ADCC mode changes from basic to average mode. In average mode, the ADCC module is configured to accumulate 16 samples and the averaged value present in the ADFLTR register is displayed on the terminal window.
In this mode, setpoint is set at 511, upper threshold to +200 and lower threshold to -200. So, when the ADC value goes below 311 (511-200) or when it goes above 711 (511+200), corresponding error message is displayed.
- Press switch (S2), the ADCC mode switches from average to burst average mode. In burst average mode, the ADCC module is configured to accumulate 16 samples sequentially (at a single stretch) for each auto conversion trigger. The averaged value of accumulated samples (present in ADFLTR register) is displayed on the terminal window.
The setpoint, upper threshold and lower threshold are same as in average mode.
- Press switch (S2), the ADCC module switches from burst average mode to Low Pass filter mode.
Select serial port, data streamer and oscilloscope options from the configuration tab of the data visualizer as shown.
- Connect the Serial port pin to the Data Streamer as shown below.
Configuring Data Streamer and Oscilloscope:
a). Select the Data Stream Config File.txt and load the file.The file can be downloaded from here
b). ADC result (ADRES) and ADC filter values (ADFLTR) are outputted
c). Connect ADRES to channel 1 and ADFLTR to channel 2 of the oscilloscope
- In low-pass filter mode, generate input signal using the function generator. The input is a DC signal with 2.5V offset, noise frequency of 100 Hz and amplitude of 200 mV(peak-peak).
- The ADCC attenuates the high frequency noise and allows only the DC signal as shown below. (deltaY of 40.84 = 200mV)
With 100 Hz noise frequency, the amplitude of the noise in the output signal has reduced to 41.6mV(peak-peak). The gain has reduced to -13.63 dB. (20 log ((8.521 * 5 / 1024)/200mV ))
With 210 Hz noise frequency (10 times the cut off frequency), the amplitude of the noise in the output signal has reduced to 18.5mV(peak-peak). The gain has reduced to -20.6 dB.(20 log ((3.803 * 5 / 1024)/200mV ))
In the above diagrams, the waveform in yellow is the raw ADRES value and waveform in green is the filtered value. Increasing the CRS value will further attenuate the AC component from the signal.
The demo provides a code example, which demonstrates the usage of PIC18FxxQ10 MCUs ADCC module and its advanced computation modes. The advanced ADCC module replaces common firmware tasks for average and filtering implementation with the hardware solution and completely avoids the firmware overhead. It performs advanced computations and filtering of data in hardware without any intervention of CPU, therefore reduces design efforts and improves system response.
The HLT module is configured in monostable mode for switch de-bounce implementation without the need of firmware logic in the application.
- Dec 4, 2018