Address error trap
Microchip's 16-bit PIC24F microcontrollers feature an on-chip mechanism to detect software errors and take corrective action
About this Code Example
Microchip's 16-bit PIC24F microcontrollers feature an on-chip mechanism to detect software errors and
take corrective action. Specifically, the ability to detect memory addressing errors is provided by means of
automatic Address Error Trap detection. Memory addressing errors may be caused by one of the following cases:
a. A misaligned data word fetch is attempted. This condition occurs when an instruction performs a word
access with the LSb of the effective address set to '1' The PIC24F CPU requires all word accesses to
be aligned to an even address boundary.
b. A bit manipulation instruction using the Indirect Addressing mode with the LSb of the effective address set to '1'.
c. A data fetch from unimplemented data address space is attempted.
d. Execution of a "BRA #literal" instruction or a "GOTO #literal" instruction, where literal is an unimplemented
program memory address.
e. Executing instructions after modifying the PC to point to unimplemented program memory addresses.
The PC may be modified by loading a value into the stack and executing a RETURN instruction.
If the application defines an Address Error Trap service routine (trap handler), the processor will vector to the
trap handler when it detects an Address Error trap. The trap in this demo will locate the error address, jump and
continue running the next instruction in CASE a, b, c and d. Because CASE e is introduced by using push and pop instruction,
which will confuse the stack including FP and PC, the trap handling routine will not be able to get the correct address
The address error trap is useful for the users to debug his firmware.
The user should note that the MPLAB?C30 C compiler will not intentionally generate any instructions that cause an
address error trap to occur. The compiler/assembler will also detect address error instances in code whenever possible.
- Jun 21, 2012
First Release to ECS