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CE030 - dsPIC SMPS ADC Triggered by Timer 1

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The dsPIC SMPS Family of Digital Signal Controllers feature an on-chip 10-bit 2 MSPS A/D Converter.

About this Code Example


This code example sets up ADC pair 0 (AN1,AN0) conversion to be triggered
by Timer 1. The input clock to the Timer module is Tcy = 1 / Fcy. In this
example, the FRC with Hi-Range is set up to run at un-tuned frequency of 
14.55 MHz. This will result in Fcy = 29.1 MHz. The input clock to the ADC
clock divider will be Fadc = 232.8 MHz

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Release History

  • Jun 15, 2012

    Version: 1.0.0

    First Release to ECS

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  • Current Version:1.0.0
  • Created:Jun 16, 2012
  • Updated:Feb 26, 2015
  • Downloads:3371
  • MPLAB Version:V8.xx or above
  • C Compiler:MCC18 v3.30 or abov
  • Development Tools:N/A
  • Supported Devices:N/A

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