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CE139 - 10-bit ADC Sampling at 2.2MSPS-1

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This test code is designed to sample channel AN0 at 2.2MSPS (single-shot acquisition) using an ADC interleaving technique. This will allow 24H/33F devices with 2 ADC modules to double the maximum sampling rate vs. a single ADC.

About this Code Example

This test code is designed to sample channel AN0 at 2.2MSPS (single-shot acquisition) using an
ADC interleaving technique. This will allow 24H/33F devices with 2 ADC modules to double the
maximum sampling rate vs. a single ADC.

The method requires 2 sample/hold amplifiers from each ADC module. You configure
both ADC, then you start one ADC and enable and wait N cycles to start the second ADC.
These N cycles will depend on ADC sampling and converting speed, for example if conversions
last 12 Tad cycles (10-bit mode), then we need to wait 6 Tad before enabling second ADC.

Upon each single conversion on ADC1, DMA ch0 reads this data and stores in DPSRAM @ 0x7800.
ADC1 Interrupt is enabled to toggle a GPIO pin (RA6) on each conversion.
DMA ch0 is set to take 32 samples from ADC1, store in DSPSRAM, autoincrement the DPSRAM pointer.
When the transfer is complete, the DMA interrupt occurs, which disables the DMA channel and ADC1.
The main() routine then reads/stores this data in the even addresses in the final 64-word result buffer.

Upon each single conversion on ADC2, DMA ch1 reads this data and stores in DPSRAM @ 0x7840.
ADC2 Interupt is enabled to toggle another GPIO pin (RA7) on each conversion
DMA ch1 is set to take 32 samples from ADC2, store in DSPSRAM, autoincrement the DPSRAM pointer.
When the transfer is complete, the DMA interrupt occurs, which disables the DMA channel and ADC2.
The main() routine then reads/stores this data in the odd addresses in the final 64-word result buffer.

There is a timing diagram that will show you what the ADCs are doing (file '2 ADC Together.doc').

Once proper synchronization is verified (i.e. equal time observed between edges on the 2 GPIO signals),
then the ADC interrupts can be disabled. The initial delay between starting the two ADCs is provided
by a REPEAT instruction in main(). 

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Release History

  • Apr 19, 2012

    Version: 1.0.0

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  • Current Version:1.0.0
  • Created:Apr 19, 2012
  • Updated:Feb 26, 2015
  • Downloads:4018
  • MPLAB Version:v8.xx or higher
  • C Compiler:c30 v3.xx or higher
  • Development Tools:Explorer 16 Demo board (R4)
  • Supported Devices:dsPIC33FJ256GP710 or dsPIC33xxxx

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