CE154 - ADC to DAC Loopback
In this example, ADC is configured to sample (AN4) at 103.16 KHz rate and the converted data is assembled in a 256-sample buffer. The captured 256 samples are output using the on-chip DAC.
About this Code Example
In this example, ADC is configured to sample (AN4) at 103.16 KHz rate and the converted data is assembled
in a 256-sample buffer. Timer 3 is setup to time-out every 9.69 microseconds (103.16 KHz rate). On every
Timer3 time-out (every Ts = 9.69 microsecs), the ADC module will stop sampling and trigger a 12-bit A/D conversion.
At that time, the conversion process starts and completes Tc = 14*Tad = 1.4 microsecs later.
When the conversion is complete, the module starts sampling again. However, since Timer3 is already on and counting,
about (Ts-Tc) = 8.29 microsecs later, Timer3 will expire again and trigger the next conversion.
The DMA is configured in continuous, ping pong mode, such that after the DMA channel has read 256 samples
into a buffer (BufferA/BufferB) a DMA interrupt is generated. The captured 256 samples are output using the on-chip DAC.
Mean while the DMA controller starts filling new ADC samples into buffer (BufferB/BufferA). Thus the two buffers are
alternately filled and released in an infinite loop.
The ADC module clock time period is configured as Tad = Tcy*(ADCS+1) = (1/40M)*(3+1) = 100 nanosecs with ADCS = 3.
Hence the conversion time for 12-bit A/D is 14*Tad = 1.4 microsecs.
- Jul 22, 2011
First upload to ECS